The scale of memory arrays has dramatically increased with technology progresses and increasing demands over the past few decades. In a conventional memory array, the readout circuit may occupy a significant portion of the entire chip area. In order to simplify the readout circuit, a number of columns are grouped as a logic column, and therefore a number of adjacent memory cells on one row are normally grouped together into a memory cell unit to share one word line or one X address. Write or read operations are performed on one single memory cell per cell unit in each clock cycle in the conventional memory array. For example, a 512×32 static random access memory (SRAM) normally consists of 128 rows, each of which includes 128 SRAM cells grouped into 32 memory cell units. That is, one memory cell unit corresponds to every four SRAM cells, and the four SRAM cells share one readout circuit.
During a write operation, an address decoder in an SRAM array receives row and column addresses over the address bus, and decodes the row addresses to enable a word line. Data on an input data port is written into one SRAM cell within a cell unit identified by the input column address while the data in the other three SRAM cells in the same memory cell unit remain the same. During a read operation, bit lines of all columns are first pre-charged, while the address decoder decodes the received addresses for the read operation. Once the address decoder completes address decoding, one word line is selected to connect the contents of one row of cell units to the bit lines while the pre-charging is terminated. Bit lines of one of the four columns are selected by the column address and then are sensed and amplified, thus completing a read operation.